SEMATECH Dictionary of Semiconductor Terms

A-Am | An-Az | B | C-Ch | Ci-Com | Con-Cz | D-De | Df-Dz | E-En | Eo-Ez | F-Fl
Fm-Fz | G | H | I | J-K | L | M-Mes | Met-Mz | N | O | P-Ph | Pi-Pq | Pr-Pz | Q | R
S-Se | Sh-So | Sp-Sta | Ste-Sz | T-Th | Ti-Tz | U-V | W-Z

"Pi-Pq"

picosecond (ps) n		second. [SEMATECH]
PID		see process-induced defect.
pigtail n		an assembly of piping used to connect a gas cylinder to piping and other components that are rigidly attached to a building structure. A pigtail can include one or more piping lines, as well as valves and other components, and normally provides sufficient flexibility to accommodate a slight variation in the location of the cylinder valve. The end of the pigtail that connects to the cylinder terminates in a Compressed Gas Association (CGA) connector. [SEMI Chemicals/Gases, Vol. 1, 1990 (no longer in print)] Also see CGA connection cap or plug.
pilot n		a wafer that is sent ahead of the parent lot to ensure that specifications are met for the remaining wafers. [SEMATECH]
pin n		in plastic and metal wafer carriers, part of a wafer carrier that enters the hole or slot of another wafer carrier for alignment when wafers are transferred. [SEMI E1-86]
pin and hole center distance from pocket center line n		in plastic and metal wafer carriers, the distance from the center line of either the pin or the hole to the closest pocket center line. [SEMI E1-86]
pinhole n		1 : minute defect or void in a film, mask, or resist, usually the result of contaminants. [SEMATECH] 2 : a small opening that extends through a covering, such as a resist coating or an oxide layer on a wafer. [SEMI P2-86]
pin grid array (PGA) n		a package or interconnection arrangement that features plug-in type electrical terminals arranged in a matrix format or an array. [SEMATECH]
pin offset n		in cofired ceramic packages, the variation in position from the center line of the pin to the center line of the braze pad to which it is mounted. [SEMI G61-94]
pin sweep n		in cofired ceramic packages, pin movement, measured with respect to a datum perpendicular to the top or bottom of the package, that passes through the designed midpoint of the pin where the pin is attached to the package (for example, pin grid arrays). The movement is viewed from the side of the package, not the ends. [SEMI G61-94]
pin-to-pin separation n		in cofired ceramic packages, the distance between adjacent pins, when measured from their center lines at the point of connection to the package. [SEMI G61-94]
pin-through hole n		a class of packages or modules soldered into plated-through holes within the second-level package or printed circuit board. [SEMATECH]
pin tweeze n		in cofired ceramic packages, pin movement, measured with respect to a datum perpendicular to the top or bottom of the package, that passes through the designed midpoint of the pin where the pin is attached to the package (for example, pin grid arrays). The movement is viewed from the ends of the package, not the side, and the pin movement is from the edges of the package in toward the center line of the package. [SEMI G61-94]
piping component(s) n		an individual component or combination of components used in a fluid or gas system for transfer of media. [SEMATECH] .
piranha n		a reactive etch solution composed of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) to remove organic contaminants from a silicon wafer or a film such as SiO2. [SEMATECH]
pit n		1 : in a wafer surface, a depression in a wafer surface that has steeply sloped sides which meet the surface in a distinguishable manner, in contrast to the rounded sides of a dimple. [ASTM F1241] Also see slip and dislocation. 2 : in semiconductor packages, plastic or ceramic, or in the leadframes, a shallow depression or crater. The bottom of the depression must be visible in order for the term to apply. A pit is formed during the component manufacture. [SEMI G61-94] Contrast chip. 3 : in flat panel display substrates, a small indentation on the glass substrate surface. [SEMI D9-94]
pitch n		the distance between a point on an image and a point on the corresponding image in an adjacent functional pattern that lies in either a row or column on a photomask or reticle. [SEMATECH] Also called periodicity and center-to-center.
pitch error n		the difference between the measured pitch and the specified pitch. [ASTM F127-84] Also called skewness.
placement n		the act of determining the exact position of a logic device on a chip/MCM/board. [1994 National Technology Roadmap for Semiconductors]
placement tolerance n		the maximum misplacement of a cassette or container by a material transport system on a tool for which the tool will operate properly. [SEMI E15-91]
planarity		see coplanarity and lead coplanarity.
planarization n		1 : a process that smooths the contours of the wafer surface by minimizing the step heights. [SEMATECH] 2 : minimizing the difference in depth of the test probe pin with respect to the bond pads of a die. [SEMATECH]
planktonic cells n		in determining surface associated biofilms of ultrapure water distribution systems, floating cells found in the bulk fluid phase. [SEMATECH]
plasma n		ionized gas used to remove resist, to etch, or to deposit various layers onto a wafer. [SEMATECH] Also see dry plasma etch.
plasma-enhanced chemical vapor deposition (PECVD) n		a deposition process in which plasma is used to lower the temperature required to deposit film onto a wafer. [SEMATECH]
plasma-enhanced TEOS oxide deposition n		a deposition process in which tetraethoxysilane (TEOS) is used as a silicon source to deposit silicon dioxide on a wafer surface. [SEMATECH]
plasma etch		see dry plasma etch.
plasma immersion ion implantation n		direct ion implantation from a plasma ambient. [SEMATECH]
plate, photographic		see photoplate.
platinum/iridium (Pt/Ir) n		in scanning tunneling microscopy, platinum and iridium alloy wire that is used to make tunneling tips. [SEMATECH]
plug n		a special deposition that fills small windows or vias for electrical connection between two layers. [SEMATECH]
pn junction n		in a semiconductor material, the point at which the conductivity changes from p-type to n-type. [SEMATECH]
pocked bead n		in an ion-exchange resin, a bead that exhibits a surface depression when viewed at 20X magnification. [SEMATECH]
pocket n		the entire area occupied by a wafer in a wafer carrier, including the entire wafer plane. [SEMI E1-86]
pocket center line n		in plastic and metal wafer carriers, the imaginary line that bisects each pocket in a wafer carrier. [SEMI E1-86]
pocket center plane n		in the design of multiple wafer carriers, the imaginary plane that bisects each pocket and is parallel to datum A. [SEMI E1.9-94]
pocket depth n		in plastic and metal wafer carriers, the distance from the pocket flat to its own pocket nose. [SEMI E1-86]
pocket flat n		in a wafer carrier, the width of the pocket along the vertical walls at its narrowest distance. [SEMI E1-86]
pocket nose n		in plastic and metal wafer carriers, the top of the material between adjacent pockets. [SEMI E1-86]
pocket nose radius n		in plastic and metal wafer carriers, the radius on the pocket nose. [SEMI E1-86]
pocket size n		1 : in plastic or metal wafer carriers, the distance between opposite pocket flats. [SEMI E1-86] 2 : in quartz or high-temperature wafer carriers, the diameter of a circle coincident to the bottom of all wafer slots (grooves for wafers) in a wafer position. [SEMI E2-93]
pocket spacing n		in plastic and metal wafer carriers, the distance between pocket center lines. [SEMI E1-86]
pocket width n		in plastic and metal wafer carriers, the greatest distance across a pocket. [SEMI E1-86]
pod n		a box having a standard mechanical interface (SMIF). [SEMI E44-95]
point defect n		a localized crystal defect such as a lattice vacancy, interstitial atom, or substitutional impurity. [ASTM F1241] Contrast with localized light scatterer.
point-like object n		in the measurement of photolithographic instruments, a circular or square form in the image, the diameter or width of which is equal to the practical resolution. [SEMI P25-94]
point of use (POU) 1 n		in gas source control equipment (GSCE), the manufacturing tool that uses the product. POU is distinguished from the GSCE by having its own design criteria, a separate function, and a physical separation from the GSCE. [SEMI F13-93] 2 adj : refers to tool-specific air emissions abatement equipment; for example, thermal oxidizers are used in some facilities to control volatile organic carbon emissions from lithography track equipment. Can also refer to a gas supply mechanism located at the tool that avoids the risk associated with transporting and piping hazardous gases such as silane. [SEMATECH]
point-to-point wafer transfer n		in cluster tools, the exchange of a wafer between a particular transport module and a particular port resource defined by a sequence of wafer exchange steps. [SEMATECH]
poison, class A n		a classification of extremely dangerous poisons such as poisonous gases or liquids of such a nature that a very small amount of the gas or vapor of the liquid mixed with air is dangerous to life. [SEMATECH]
poison, class B n		a classification of liquid, solid, paste, or semisolid substances, other than class A poisons or irritating materials, known or presumed on the basis of animal tests to be so toxic to man as to afford a hazard to health during transportation. [SEMATECH]
Poisson distribution n		a probability distribution, the mean and variance of which have a common value k, and the frequency of which is , for x=0, 1, 2,.... [SEMATECH]
polarization n		in optics, the term used to describe the orientation of the electric field vector in an electromagnetic wave. [ASTM F1241]
polarized light n		in optics, light that exhibits different properties in different directions at right angles to the line of propagation. [ASTM F1241]
polar transmission n		a method of transmitting teletypewriter signals when current flows in opposite directions. Direct current flowing in one direction identifies the marking signal, and an equal current flowing in the opposite direction identifies the spacing signal. [SEMATECH]
poly		see polycrystalline silicon.
polycide n		a material formed by reaction of polysilicon with a metal, most often applied in the gate structure of a metal-oxide semiconductor transistor when polysilicon gate electrode is reacted with a deposited refractor metal layer to reduce the electrical resistance of the gate. [1994 National Technology Roadmap for Semiconductors]
polycrystalline adj		describes a form of semiconductor material made up of randomly oriented crystallites and containing large-angle grain boundaries, twin boundaries, or both. [SEMI M10-89 and ASTM F1241] Contrast single crystal. Also see amorphous silicon.
polycrystalline silicon (poly) n		1 : a nonporous form of silicon made up of randomly oriented crystallites or domains, including glassy or amorphous silicon layers. [ASTM F399-88] 2 : silicon formed by chemical vapor deposition from a silicon source gas or other methods and having a structure that contains large-angle grain boundaries, twin boundaries, or both. [SEMI M16-89] Also called poly and polysilicon. Contrast amorphous silicon and single crystal.
polymorphism n		the ability to hide different implementations behind a common interface, simplifying the communications among objects. For example, defining a unique print method for each kind of document in a system would allow any document to be printed by sending the message print, without concern for how that method was actually carried out for a given document. [SEMATECH]
polysilicon (poly)		see polycrystalline silicon.
polysilicon haze n		a high density of submicrometer particles deposited on polysilicon film during the polysilicon deposition process. [SEMATECH]
polystyrene latex sphere n		consistently sized and characterized spheres that represent particles on the wafer surface, but may not be indicative of actual particles encountered in the fab environment. These spheres are used to calibrate the particle counter response curve. [SEMATECH]
population n		a group of devices that have exactly the same properties; that is, all members are indistinguishable, one from another. [SEMATECH]
porous surface n		in cofired ceramic packages, an uncompacted ceramic surface often showing fine pits. [SEMI G61-94]
port n		1 : a terminal of a semiconductor device or component at which information can be extracted or inserted. [SEMATECH] 2 : in automated material movement, a point on the equipment at which a change of equipment ownership of a transfer object occurs, including any dedicated mechanisms that either prepare for, facilitate, or are capable of interfering with the transfer. [Adapted from SEMI E32-94] Also see tool.
port assembly n		an assembly of the port plate and port door that includes the guide rails, registration pins, latch pins, latch cavities, and box hold-down latches. [SEMI E19.4-94]
port door n		a door for the port plate opening that provides a mating surface for the bottom of the box door when the box is in place on the port plate. The port door contains the registration pins and the box door latch pins. [SEMI E19.4-94]
port plate n		a horizontal mating surface for the base of the box that provides a seal surface to the bottom surface of the box perimeter. The port plate contains the guide rails and the latch pins. [SEMI E19.4-94]
port resource server n		in a cluster tool control system, a server associated with an individual attached module at an individual interface plane, which provides the services necessary to perform point-to-point wafer transfers between the transport module associated with that interface plane and the attached module. [SEMI MESC]
position reference point n		in cluster tools, a location defined in an attached module's local coordinate system, through which an end effector will pass during a wafer exchange sequence. [SEMATECH]
positive mask		see photomask, positive.
post-etch		see linewidth, etched.
post-exposure bake (PEB) n		a bake after expose and prior to develop to diffuse the photoactive component of the resist; minimizes standing waves and ensures a clean develop. [SEMATECH]
post-metallization n		in pressed ceramic pin grid array packages, the process by which metallization is applied to a body (substrate) after the body has been fully sintered. [SEMI G33-90]
post-process treatment chamber (PTC) n		the chamber(s) within the process equipment in which wafers are treated after actual wafer processing (for example, a post-process rinse and dry chamber). [SEMATECH]
potassium hydroxide (KOH) n		a strong, poisonous, and corrosive base that absorbs carbon dioxide from the air. [SEMI C1.14-90]
POU		see point of use.
power dissipation (PH) n		in the measurement of the thermal resistance of a semiconductor device, the heating power applied to the device to cause a junction to specified reference point (possibly case) temperature difference. PH is measured in watts. [SEMI G38-87] Also see integrated circuit and package.
power management n		design techniques that allow power to be controlled or reduced to achieve specific design goals. These could include overall chip dissipation or local affects such as electromigration or voltage drop. [1994 National Technology Roadmap for Semiconductors]

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