ISMI News

International SEMATECH to Host Standards Technical Education Program at SEMICON West

Austin, TX (8 June, 2004) – International SEMATECH Mask Strategy Program Manager Scott Hector will present a Standards Technical Education Program (STEP) on extreme ultraviolet (EUV) lithography masks from 8 a.m. – 12 p.m. on July 13 at the San Francisco Marriott Hotel during SEMICON West.

While EUV is emerging as a potential lithography solution for the sub-45 nm technology node defined by the International Technology Roadmap for Semiconductors (ITRS), EUV mask standards development has been in progress with help from SEMATECH over the last five years. SEMI® standards P37, P38 and P40 contain requirements for EUV mask substrates and blanks, and additional standards (on mounting, handling, storage etc.) are being defined to support EUV mask infrastructure. This half-day program will describe the rationale for each requirement in these standards.

This program is designed for anyone with an interest in EUV mask technology, especially IC manufacturers, equipment suppliers for EUV exposure tools and mask fabrication, and suppliers of subsystems for EUV mask fabrication tools.

Hector—together with colleagues Thomas White (International SEMATECH), Roxann Engelstad (University of Wisconsin), Pei-Yang Yan (Intel), Eric Gullikson (Lawrence Berkeley National Lab)—will present a history and overview of the EUV mask SEMI standards and discuss in detail the following:

  • Overlay and critical dimension (CD) control error budgets to meet ITRS requirements for <=45-nm nodes
  • Relationships among various SEMI standards for EUV masks
  • EUV mask substrate defect, thermal expansion, flatness, and roughness requirements, and how they affect overlay and CD control (SEMI P37
  • EUV mask blank multilayer and absorbing layer requirements and how they affect overlay and CD control (SEMI P38)
  • Effects of EUV mask flatness on overlay, including the rationale for and requirements of a standard mounting method for EUV masks (SEMI P40)
  • EUV mask patterning approaches and issues
  • Standards under development for low-defect EUV mask handling
  • Next steps and future evolution of the standards

For more information about the program, see Standards Technical Education Program (STEP): EUV Lithography Masks on the SEMI website.